library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity logicals is
generic (N:integer:=32);
port (	R1	: in   std_logic_vector (N-1 downto 0);
		R2	: in   std_logic_vector (N-1 downto 0);
		S	: in   std_logic_vector (3 downto 0);
		L	: out std_logic_vector (N-1 downto 0)
	);
end logicals;

architecture Structural of logicals is
begin

LOGICALS_GEN:for i in 0 to N-1 generate
	L(i) 	<= 	(S(0) and (not R1(i)) and (not R2(i)))	or
			(S(1) and (not R1(i)) and R2(i))		or
			(S(2) and (R1(i) and (not R2(i))))		or
			(S(3) and (R1(i) and R2(i)))			;
end generate;

end Structural;

